Plural Distributed PBS with Both Voltage and Current Sensing SA for J-Page Hierarchical NAND Array's Concurrent Operations

USPTO Patent Application US 2017/0352424 A1
Application Date: Dec. 7th, 2017


Provided are several preferred options of 3D hierarchical NAND arrays being formed in a (2D DL//3D LBL)⊥(3D CSL//3D WL) scheme and their associated 2D PBs are preferably formed right below...
Application Number:
International Classification:
G11C 16/10 (20060101); G11C 16/04 (20060101); G11C 11/56 (20060101); G11C 16/34 (20060101); G11C 16/26 (20060101)
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What is claimed is:

1. A 3D hierarchical NAND arrays comprising: a plurality of divided 3D sub-arrays for nLC storage, a plurality of 3D N-bit Cstring-based DCRs with minimum memory capacity to store 3×2n pages of program data when a 3-WL rotational nLC program scheme is adopted, and a plurality of distributed N-bit PBs with...



1. This application is the continuation of many U.S. Provisional and patent applications filed by same inventor of the present invention are commonly assigned and incorporated by reference herein for all purposes.
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